1. Field of the Invention
The present disclosure relates to a method of automatic deposition profile targeting and control using feedback data from an advanced polish endpoint system, and, more particularly, to automatic deposition profile targeting with a combined deposition/polishing apparatus which obtains matching deposition and subsequent polishing profiles.
2. Description of the Related Art
The demand for an improved efficiency of manufacturing processes of highly integrated circuits in order to save manufacturing costs, as well as the demand for products having a higher performance, led to a new material deposition and removal technique. For example, conventionally, a layer of material is deposited by, for instance, vapor deposition or sputtering. Subsequently, the deposited material is patterned with photoresist and etching technologies. There are, however, cases where it is more efficient not to use photoresist patterning techniques and classical anisotropic and unisotropic etching technologies.
One of these cases is the copper damascene integration technique that has been developed in response to the demand for higher integration, higher clock frequencies and smaller power consumption in microprocessor technology. Since copper is a better conductor than the usually used aluminum, chips using the copper wiring technology may have smaller metal components and use less energy to pass electricity through them. These effects lead to a high performance of the integrated circuits.
The transition from aluminum to copper required, however, significant developments in fabrication techniques. Since volatile copper compounds do not exist, copper cannot be readily patterned by photoresist masking and plasma etching such that a new technology for patterning copper had to be developed, which is known as a copper damascene process. In this process, the underlying silicon dioxide insulating layer is patterned with open trenches where the conductor should be filled in. A thick coating of copper that significantly overfills the trenches is deposited on the insulator and chemical mechanical planarization (CMP), also known as chemical mechanical polishing, is used to remove the excess copper to the top level of the trench.
Since copper may not be deposited efficiently by physical vapor deposition, for example, by sputter deposition, with a layer thickness on the order of 1 μm and more, electroplating of copper and copper alloys is the currently preferred deposition method of forming metallization layers. Although, electroplating of copper is a well-established technique, reliably establishing copper over large diameter substrates having a patterned surface including trenches and wires is a challenging task for process engineers. At a first glance, it appears to be advantageous that metal thickness profile across the substrate surface may be formed as uniformly as possible. However, post-plating processes may require a differently shaped profile to assure proper device functionality of the completed integrated circuits. Currently, there is no effective copper dry etching method because of problems removing low volatility copper compounds. Presently, chemical mechanical polishing (CMP) is used for removing excess copper. Since the CMP process is per se a highly complex process frequently exhibiting an intrinsic process non-uniformity, i.e., a non-uniform removal rate across the substrate surface, it may be preferable to adapt the metal thickness profile to the post-plating process to achieve in total an improved process uniformity after completion of the post-plating process. Therefore, electroplating tools are often configured so as to allow a variation of the metal profile, for instance, by using multiple anodes on an electrochemical deposition (ECD) copper plating tool.
In conclusion, in copper damascene integration schemes for an optimal chemical mechanical polishing process, a metal deposition with corresponding plating profile is necessary for process stabilization and optimization. That means that, in different zones on a wafer, there is required deposition of different metal thicknesses. The deposition tool must be capable to actively influence the deposition profile, e.g., using multiple anodes on an ECD copper plating tool. The goal for optimal deposition processes is to match the inverse polish removal profile and to actively compensate influences like consumable aging and process line variations. If the optimal deposition profile and the thickness is not provided, the combined deposition and CMP process will provide different material thicknesses within a wafer diameter, causing a strong variation within the wafer for device relevant product parameters.
The above problem is illustrated in FIGS. 1a-1b. FIG. 1a illustrates the case where the deposition profile does not match the inverse polish removal profile. In contrast thereto, FIG. 1b illustrates a case where the deposition profile matches with the inverse polish removal profile.
Back to FIG. 1a, a target profile is shown indicated by broken line 7. Line 1 illustrates the thickness of the deposited material before starting the polishing process (time 0). Line 2 illustrates the thickness of the deposited material at time 1 after the polishing process has been started. As can be seen, the profile mismatch becomes more distinctive when proceeding with the polishing process, i.e., the edges of the deposited material become sharper and the thickness inhomogeneity across the radius (−R to R) becomes larger. At the end of the polishing, indicated by line 3, only the edges of the deposited material meet the target thickness. In the central region of the deposited material, the thickness is too small.
In contrast thereto, FIG. 1b shows an optimal profile match between the deposition profile and the polishing profile. Line 4 shows the material thickness before starting the polishing process at time 0. Line 5 shows the material thickness after a certain time of polishing. As it can be seen, the thickness inhomogeneity has not become larger. At the end of the polishing process, the thickness of the deposited material, indicated by line 6, meets the target thickness indicated by broken line 7.
It is clear from FIG. 1 that devices in the middle of a wafer (radius 0) must have metal layer thicknesses that are significantly different than devices at the edge of a wafer (radius R). To the contrary, according to FIG. 1b, the thickness of the metal layer on the devices in the middle of the wafer is expected to be the same as in the edge region.
In order to avoid a mismatch between the deposition profile and the polishing profile, there are known so-called static solutions based on a given or assumed fixed CMP/polish removal profile in combination with a statically adjusted deposition profile. Alternatively, a static solution may be based on a fixed deposition shape like a defined bowl, dome or even for a flat profile within a wafer diameter in combination with a respectively adapted static removal profile.
These static methods are illustrated in FIGS. 2a-2b. FIG. 2a illustrates how a combined deposition/polishing process is set up and FIG. 2b illustrates carrying out the combined deposition/polishing production process.
Before a combined deposition/polishing process may be used for production of product wafers, appropriate tool settings have to be determined. Conventionally, this is done by running test wafers as illustrated in FIG. 2a. In FIG. 2a, a deposition tool 10 deposits a certain material on a test wafer using initial settings 11 for the deposition tool. Subsequently, a thickness profile of the deposited material may be measured in a profile measurement tool 15. Subsequently, excess material is removed in the polishing tool 13. On most enhanced CMP/polish tools there are endpoint systems available, which are illustrated in FIG. 2a as endpoint measurement tool 12. The endpoint measurement tool 12 determines the actual thickness profile of the remaining material of the layer currently polished. For choosing initial settings 14 of the polishing tool 13, the results of the profile measurement tool 15 may be used. If the endpoint measurement tool 12 results in a mismatch between the deposition profile and the polishing profile, it has to be decided as to whether adjusting the polishing tool settings 14 is sufficient to correct the mismatch. At the beginning of the process of finding appropriate tool settings, mostly the mismatch is too large such that it cannot be compensated for by the polishing tool alone. Therefore, adjusting the deposition tool settings 11 has to be considered as well. In this case, the endpoint measurement tool 12 provides a polishing profile and test wafer runs are carried out with successively changing the deposition tool settings 11 until the measurements taken by the profile measurement tool 15 indicate that the difference between the measured material thickness profile and the inverse polishing profile is smaller than a predetermined value. Fine adjustments may be carried out by modifying the polishing tool settings under the control of the endpoint measurement tool 12.
FIG. 2b shows the wafer flow and data flow under production conditions. The settings 11 and 14 for the deposition tool 10 and the polishing tool 13 are assumed to be given. The settings 11 for the deposition tool 10 will be fixed and smaller process fluctuations may be compensated for, for instance, by adjustment of the settings 14 of the polishing tool 13 due to the results of the endpoint measurement tool 12. The adjustment then becomes effective in the next wafer run. Since the deposition tool settings are treated fixed, this method is called a static method.
It has to be noted that the characterization of the process illustrated in FIGS. 2a-2b needs to be done individually per layer and product if there are significant differences in percentages of open areas, die sizes and wafer stepping. All these efforts lead to a consumption of a certain amount of wafers to find the right shaping, which adds costs and cycle time. The CMP process is very consumable dependent. Therefore, a one-time snapshot is not always relevant for the whole population of product wafers. Additionally, there may be an individual operator and/or engineering dependence variable associated with these processes. A further drawback of the static method is that the process fluctuations cannot be compensated for efficiently. For instance, the electrolyte concentration in the case of electrochemical deposition of copper may change with time, which leads to a change of the plating profile. Anodes or cathodes might corrode with time such that the plating settings become inadequate. Chemical mechanical polishing conditions may change due to deterioration of the tool characteristics. As a consequence, additional qualification runs of test wafers have to be carried out in order to re-adjust the tool settings, i.e., the deposition tool and the CMP tool.
In view of the global market forces to offer high quality products at low prices, it is thus important to improve yield and process efficiency to minimize production costs. In manufacturing modern integrated circuits, 500 or more individual processes may be necessary to complete the integrated circuit, wherein failure in a single process step may result in a loss of a complete integrated circuit. It is therefore crucial for manufacturing integrated circuits that each individual step reliably has the desired result requiring the least possible resources.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.